Timer V is an 8-bit timer based on an 8-bit counter capable of counting external events. Two compare match registers are available to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin (P17), enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input.
There are seven possible sources of clock inputs for timer V. Six of these are derived from the system clock with divisors of 128, 64, 32, 16, 8 or 4. The other source is the TMCIV pin (P75).
The two compare match registers, TCORA and TCORB can be used to clear the counter and optionally to stop it. An external signal on TMRIV (P74) can also be used to clear the timer
Either of the compare registers, or a timer overflow can generate an interrupt.
A single output pin, TMOV (P75), can be controlled by the compare match registers to allow single or repeated pulses with arbitrary mark-space ratios. This also allows a single channel of PWM to be generated.
Counting can be initiated by a trigger on TRGV (P17) which allows the counting or timing of events as well as triggered or synchronised pulse outputs. The rising edge, falling edge, or both edges of the TRGV input can be selected.
Timer V is a very flexible device and consequently has many configuration settings and registers. The registers used ar:
• Timer counter V (TCNTV)
This 8 bit counter can be read or written at any time
• Timer constant register A (TCORA)
• Timer constant register B (TCORB)
Both these compare match registers are compared with TCNTV at all times. When the register and TCNTV contents match, CMFA or CMFB, as appropriate, are set to 1 in TCSRV. interrupts can be generated if CMIEA (or CMIEB) is also set to 1 in TCRV0.
• Timer control register V0 (TCRV0)
TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request. Under GNUH8, the control structures are:
TV.TCRV0.BIT.CMIEB; // 0..1 interrupt on compare match B TV.TCRV0.BIT.CMIEA; // 0..1 interrupt on compare match A TV.TCRV0.BIT.OVIE ; // 0..1 interrupt on overflow TV.TCRV0.BIT.CCLR ; // 0..3 counter clear source TV.TCRV0.BIT.CKS ; // 0..7 clock source
• Timer control register V1 (TCRV1)
TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV.
TV.TCRV1.BIT.TVEG; // 0..3:select trigger edge TV.TCRV1.BIT.TRGE; // 0..1:trigger enable TV.TCRV1.BIT.ICKS; // 0..1:combine with TCRV0.BIT.CKS
• Timer control/status register V (TCSRV)
TCSRV incicates the status flags and control outputs for timer V
TV.TCSRV.BIT.CMFB; // compare match flag B TV.TCSRV.BIT.CMFA; // compare match flag A TV.TCSRV.BIT.OVF ; // overflow flag TV.TCSRV.BIT.OS ; // output select
There are two possible output actions for each compare match event. Each event can be set to do nothing, set TMOV, clear TMOV or toggle TMOV. That is sicteen possible compbinations wrapped up in TV.TCNTV.BIT.OS
Pulse Output with Arbitrary Duty Cycle
Required: a pulse train with a period of 100us and a duty cycle of 33%.
// clear counter on compare match A TV.TCRV0.BIT.CCLR = 0x01; // set TMOV on compare match A and // clear TMOV on compare match B TV.TCSRV.BIT.OS = 0x06; // choose the clock source as ø/16 TV.TCRV0.BIT.CKS = 0x02; // set the period TV.TCORA = 99; // and the pulse width TV.TCORB = 32;
Note that the compare match counts start from zero so we use N-1 in the register